In previous work, the authors presented a 3D hexagonal wireless direct-interconnect\nnetwork for a massively parallel computer, with a focus on analysing processor utilisation.\nIn this study, we consider the characteristics of such an architecture in terms of link utilisation\nand power consumption. We have applied a store-and-forward packet-switching algorithm to\nboth our proposed architecture and a traditional wired 5D direct network (the same as IBM�s\nBlue Gene). Simulations show that for small and medium-size networks the link utility of the\nproposed architecture is comparable with (and in some cases even better than) traditional 5D\nnetworks. This work demonstrates that there is a potential for wireless processing array concepts to\naddress High-Performance Computing (HPC) challenges whilst alleviating some significant physical\nconstruction drawbacks of traditional systems.
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